Why we are using 2 state data type in system verilog?

2-state data types is used to improve simulator performance and reduce memory usage, compared with variables declared as 4-state types.

2-state data type :-

bit (FYI,by default unsigned),

byte,

int,

shortint,

longint,

real.

4-state data type :-

time (FYI,by default unsigned),

integer,

logic (FYI,by default unsigned),

reg (FYI,by default unsigned).