Friday, May 25, 2018

What is the difference between verilog continuous and procedural assignment?

The best way to understand the verilog continuous and procedural assignment is by looking at the examples.

Continuous Assignment Statement Examples
assign output1 = x1 & x2 ;
wire output1 = p1 & p2 ;

Procedural Assignment Statement Examples

always @ (posedge clk)
  xyz <= in1 & in2 ; 

always @ ( posedge clk or negedge reset) 
if ( !reset) 
  xyz <= 0 ; 
  xyz = in1;

Here are the key points to know about the difference in the Continuous and procedural assignment statements

1. The continuous assignment statement is used to infer combinatorial logic. The procedural assignment statement is used to infer the combinatorial as well as the sequential logic including flip flops and latches.

2. The continuous assignment statement assigns value primarily to nets while the
procedural assignment statement assigns values primarily to reg element.

3. The variables are driven to the output continuously to the output in the continuous assignment statement. In the procedural assignment statement, the results of the calculation are stores in a variable.

Thursday, April 27, 2017

SystemVerilog assertions (SVA) - $assertkill or $assertoff or $asserton

$assertoff - used to disable all assertions but allows currently active assertions to complete before being disabled.
$assertkill - used to kill and disable all assertions including currently active assertions.
$asserton - used to turn all assertions back on

Monday, February 27, 2017

What is exact difference between $cast as a task and function?

This terminology originally comes from Verilog where a function call always had a return value and could only be used as part of an expression, and a task call never had a return value and could only be used as a simple statement. Now System Verilog allows functions defined with no return value (a void return type), and allows functions with return values to be called as simple statements, and the return value is just thrown away.

So when we say $cast called as a function, we mean it is called as part of an expression

if ($cast(a_handle, b_handle)) something;

and when $cast is called as a task, it is just a simple statement.

$cast(a_handle, b_handle);

The only difference between the two is when the cast fails. Called as a task, it generates a run-time error, which would be consider a testing error.

When called as a function, it never generates an error, it just returns 1 for success and 0 for unsuccessful. You would use a $cast as a function when you have a class handle and want to know what the type of the class object is. Normally, you have a base class variable and want to try casting it to an extended class variable type.

Wednesday, February 22, 2017

Systemverilog Assertions Overview

Wednesday, February 8, 2017

Why system verilog does not allow always block in program block?

The program block came from the Vera verification language that was donated to SystemVerilog. In Vera, a program was a single procedure that represented the "test". Your test was started at time 0 and when the test terminated, the program terminated the simulation. If you needed multiple test threads, you either had to use the fork statement to start it, or use multiple programs. When the last program terminated, the simulation terminated.

As part of the integration with SystemVerilog, the program was turned into a module-like construct with ports and initial blocks are now used to start the test procedure. Because an always block never terminates, it was kept out of the program block so the concept of test termination would still be there.

Today, most people do not utilize this termination feature because the OVM/UVM have their own test termination mechanisms. The program block is no longer a necessary feature of the language other than to help people converting over from Vera to SystemVerilog.

Monday, January 30, 2017

Why we are using 2 state data type in system verilog?

2-state data types is used to improve simulator performance and reduce memory usage, compared with variables declared as 4-state types.

2-state data type :-
bit (FYI,by default unsigned),

4-state data type :-
time (FYI,by default unsigned),
logic (FYI,by default unsigned),
reg (FYI,by default unsigned).

What is logic and reg in System verilog?

SystemVerilog improves the classic reg data type so that it can be driven by continuous assignments, gates, and modules, in addition to being a variable. It is given the synonym logic so that it does not look like a register declaration. A logic signal can be used anywhere a net is used, except that a logic variable cannot be driven by multiple structural drivers, such as when you are modeling a bidirectional bus.

You can use the logic type to find netlist bugs as this type can only have a single driver. Rather than trying to choose between reg and wire, declare all your signals as logic, and you’ll get a compilation error if it has multiple drivers. Of course, any signal that you do want to have multiple drivers, such as a bidirectional bus, should be declared with a net type such as wire.