Sunday, June 24, 2018

What are Method Overriding and Method Overloading? What is the difference between the two?

Method overloading is the ability of the functions with same names to be defined multiple times with different set of parameters.

For Example: A function add() can be defined in three formats as shown below. Based on the type and number of arguments passed when the function is called, the correct definition will be picked up.

1) function add (int operand1, int operand2);
2) function add (int operand1, int operand2, int operand3)
3) function add (float operand1, float operand2)

Method overriding is the ability of the inherited class redefining the virtual method of the base class.
Method overriding is supported in most of the object oriented programming languages.
However, unlike C++, method overloading is not supported in SystemVerilog language.
SystemVerilog language only supports method overriding in terms of virtual methods and derived classes. For Example: A base class can define a function called compare() which compares two data members of its class as follows

class BaseClass;
   int a, b;
   virtual bit function compare();
      if(a==b) return 1;

A derived class can override this definition based on new data members as shown below:

class DerivedClass extends BaseClass;
   int c;
   function compare();
       if((a==b) && (a==c)) return 1;

What are public, private and protected members?

These are different access attributes for class members.

1) Private data members of a class can only be accessed from within the class. These data members will not be visible in derived classes

2) Public members can be accessed from within the class as well as outside the class also. These are also visible in derived classes

3) Protected data members are similar to private members in the sense that they are only accessible within the class. However unlike private members, these are also visible in derived class.

Saturday, June 23, 2018

Why AHB does not cross 1KB address boundary?

In AHB, The minimum address space that can be allocated to a single slave is 1KB. All masters are designed so that they do not perform incrementing transfers over a 1KB address boundary. This ensures that a burst never crosses an address decode boundary.

Friday, May 25, 2018

What is the difference between verilog continuous and procedural assignment?

The best way to understand the verilog continuous and procedural assignment is by looking at the examples.

Continuous Assignment Statement Examples
assign output1 = x1 & x2 ;
wire output1 = p1 & p2 ;

Procedural Assignment Statement Examples

always @ (posedge clk)
  xyz <= in1 & in2 ; 

always @ ( posedge clk or negedge reset) 
if ( !reset) 
  xyz <= 0 ; 
  xyz = in1;

Here are the key points to know about the difference in the Continuous and procedural assignment statements

1. The continuous assignment statement is used to infer combinatorial logic. The procedural assignment statement is used to infer the combinatorial as well as the sequential logic including flip flops and latches.

2. The continuous assignment statement assigns value primarily to nets while the
procedural assignment statement assigns values primarily to reg element.

3. The variables are driven to the output continuously to the output in the continuous assignment statement. In the procedural assignment statement, the results of the calculation are stores in a variable.

Thursday, April 27, 2017

SystemVerilog assertions (SVA) - $assertkill or $assertoff or $asserton

$assertoff - used to disable all assertions but allows currently active assertions to complete before being disabled.
$assertkill - used to kill and disable all assertions including currently active assertions.
$asserton - used to turn all assertions back on

Monday, February 27, 2017

What is exact difference between $cast as a task and function?

This terminology originally comes from Verilog where a function call always had a return value and could only be used as part of an expression, and a task call never had a return value and could only be used as a simple statement. Now System Verilog allows functions defined with no return value (a void return type), and allows functions with return values to be called as simple statements, and the return value is just thrown away.

So when we say $cast called as a function, we mean it is called as part of an expression

if ($cast(a_handle, b_handle)) something;

and when $cast is called as a task, it is just a simple statement.

$cast(a_handle, b_handle);

The only difference between the two is when the cast fails. Called as a task, it generates a run-time error, which would be consider a testing error.

When called as a function, it never generates an error, it just returns 1 for success and 0 for unsuccessful. You would use a $cast as a function when you have a class handle and want to know what the type of the class object is. Normally, you have a base class variable and want to try casting it to an extended class variable type.

Wednesday, February 22, 2017

Systemverilog Assertions Overview