Monday, January 30, 2017

What is logic and reg in System verilog?

SystemVerilog improves the classic reg data type so that it can be driven by continuous assignments, gates, and modules, in addition to being a variable. It is given the synonym logic so that it does not look like a register declaration. A logic signal can be used anywhere a net is used, except that a logic variable cannot be driven by multiple structural drivers, such as when you are modeling a bidirectional bus.

You can use the logic type to find netlist bugs as this type can only have a single driver. Rather than trying to choose between reg and wire, declare all your signals as logic, and you’ll get a compilation error if it has multiple drivers. Of course, any signal that you do want to have multiple drivers, such as a bidirectional bus, should be declared with a net type such as wire.

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