ASIC Experts
A System verilog and UVM Fundamental Guide...
Showing posts with label
run_test
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Showing posts with label
run_test
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Tuesday, January 3, 2017
How uvm phases initiate?
UVM phases initiate by calling run_test(“test”) in top module. When run_test() method call, it first create the object of test top & then call all phases.
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