UVM Phases is used to control the behavior of simulation in a systematic way & execute in a sequential ordered to avoid race condition. This could also be done in system verilog but manually.
List of UVM Phases:
List of UVM Phases:
- build_phase
- connect_phase
- end_of_elaboration_phase
- start_of_simulation_phase
- run _phase (task)
Sub Phases of Reset Phase: - pre_reset_phase
- reset_phase
- post_reset_phase
- pre_configure_phase
- configure_phase
- post_configure_phase
- pre_main_phase
- main_phase
- post_main_phase
- pre_shutdown_phase
- shutdown_phase
- post_shutdown_phase
- extract_phase
- check_phase
- report_phase
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