Friday, January 20, 2017

What is Scope Resolution Operator :: in system Verilog ?

The class scope operator :: is used to specify an identifier defined within the scope of a class.classes and other scopes can have the same identifiers, the scope resolution operator uniquely identifies a member of a particular class.

Class Resolution operator allows access to static members (class properties and methods) from outside the class, as well as access to public or protected elements of a super classes from within the derived classes.

In the Below example,
Static class member is accessed using class resolution operator ::
class packet;
         bit [31:0] addr;
  static bit [31:0] id;
  function display(bit [31:0] a,b);
    $display("Values are %0d %0d",a,b);
module top;
  int id=10;
  initial begin
    packet p;
    = new();
    packet::id = 20;

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