What is Scope Resolution Operator :: in system Verilog ?

The class scope operator :: is used to specify an identifier defined within the scope of a class.classes and other scopes can have the same identifiers, the scope resolution operator uniquely identifies a member of a particular class.

Class Resolution operator allows access to static members (class properties and methods) from outside the class, as well as access to public or protected elements of a super classes from within the derived classes.

In the Below example,
Static class member is accessed using class resolution operator ::

//class

class packet;          bit [31:0] addr;   static bit [31:0] id;     function display(bit [31:0] a,b);     $display("Values are %0d %0d",a,b);   endfunction endclass   module top;   int id=10;   initial begin     packet p;     p = new();     packet::id = 20;     p.display(packet::id,id);   end endmodule